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a multiformat hdtv encoder with three 11-bit dacs input formats ycrcb in 2x10-bit (4:2:2) or 3x10-bit (4:4:4) format compliant to smpte-274m (1080i), smpte-296m (720p) and any other high definition standard using async timing mode rgb in 3x10 bit 4:4:4 format output formats yprpb hdtv (eia 770.3) rgb levels compliant to rs-170 and rs-343a programmable features internal testpattern generator with color control y/c delay (+/-) individual dac on/off control vbi open control prelim rev d 2510 - information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. functional block diagram preliminary technical data adv7197 general description general description general description general description general description the adv7197 is a triple high speed, digital-to-analog encoder on a single monolithic chip. it consists of three high speed video d/a converters with ttl compatible inputs. the adv7197 has three separate 10-bit wide input ports which accept data in 4:4:4 10-bit ycrcb or rgb or 4:2:2 10-bit ycrcb. this data is accepted in hdtv format at 74.25mhz or 74.1758mhz. for any other high defini- tion standard but smpte274m or smpte296m the async timing mode can be used to input data to the adv7197. for all standards, external horizontal, vertical and blanking signals or eav/sav codes control the insertion of appropriate synchronisation signals into the digital data stream and therefore the output signals. * adv is a registered trademark of analog devices, inc. * adv is a registered trademark of analog devices, inc. * adv is a registered trademark of analog devices, inc. * adv is a registered trademark of analog devices, inc. * adv is a registered trademark of analog devices, inc. one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 2000 2 wire serial mpu interface single supply +5v/+3.3 v operation 52-pqfp package applications hdtv display devices hdtv projection systems digital video systems high resolution color graphics image processing/ instrumentation digital radio modulation/ video signal reconstruction the adv7197 outputs analog yprpb hdtv complying to eia 770.3 or rgb complying to rs-170/rs-343a. the adv7197 requires a single +5v/3.3v power supply, an optional external 1.235 v reference and a 74.25mhz (or 74.1758mhz) clock. the adv7197 is packaged in a 52-pin pqfp package. 4:2:2 to 4:4:4 dac control block vref rset comp 11-bit dac 11-bit dac 11-bit dac dac a (y) dac b dac c sync generator timing generator testpattern generator & delay i2c mpu port horizontalsync vertical sync bla nking clkin reset y0-y9 cr0-9 cb 0-9 4:2:2 to 4:4:4 preliminary technical data
prelim rev d adv7197 preliminary information ?2? 5v specifications parameter parameter parameter parameter parameter min min min min min typ typ typ typ typ max max max max max units units units units units test conditions test conditions test conditions test conditions test conditions 1 1 1 1 1 static performance resolution (each dac) 11 bits integral nonlinearity dac a 3 1.3 lsb differential nonlinearity dac a 3 0.9 lsb guaranteed monotonic integral nonlinearity dac b,c 3 1.3 lsb differential nonlinearity dac a 3 0.9 lsb guaranteed monotonic digital outputs output high voltage, v oh 2.4 v output low voltage, v ol 0.4 v three state leakage current 0.05 a vin=0.4v three state output capacitance tba p f digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 v input current, i in tba a input leakage current 0.02 ua vin=0.4v or 2.4v input capacitance, c in tba pf analog outputs output current (dac b, c) 2.66 ma output current (dac a) 4.33 ma dac to dac matching 1.5 % dac a,b,c output compliance range, v oc tba v output impedance, r out tba kw output capacitance, c out tba pf i out = 0 ma voltage reference(ext. and int.) reference range, v ref 1.235 v power requirements 4 idd 1 66 ma iaa 2 11.25 ma power supply rejection ratio 0.02 % / % notes 1 idd or the circuit current, is the continuous current required to drive the digital core 2 iaa is the total current required to supply all dacs including the vref circuitry 3 guaranteed by characterisation 4 all dacs on specifications subject to change without notice (v aa = + 5v 5%, v ref = 1.235 v, r set = 2470 w , r load =300 w. all specifications t min to t max (0 o c to 70 o c) unless otherwise noted, tj max = 110 o c. preliminary technical data
prelim rev d ?3? adv7197 preliminary information (v aa = + 3.3v 5%, v ref = 1.235 v, r set = 2470 w , r load =300 w. all specifications t min to t max (0 o c to 70 o c) unless otherwise noted, tj max = 110 o c. 3.3v specifications 1 parameter parameter parameter parameter parameter min min min min min typ typ typ typ typ max max max max max units units units units units test conditions test conditions test conditions test conditions test conditions 1 1 1 1 1 static performance resolution (each dac) 11 bits integral nonlinearity dac a 1.3 lsb differential nonlinearity dac a 0.9 lsb guaranteed monotonic integral nonlinearity dac b,c 1.3 lsb differential nonlinearity dac a 0.9 lsb guaranteed monotonic digital outputs output high voltage, v oh 2.4 v output low voltage, v ol 0.4 v three state leakage current 0.05 a vin=0.4v three state output capacitance tba p f digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 v input current, i in tba a input leakage current 0.02 ua vin=0.4v or 2.4v input capacitance, c in tba pf analog outputs output current (dac b, c) 2.66 ma output current (dac a) 4.33 ma dac to dac matching 1.5 % dac a,b,c output compliance range, v oc tba v output impedance, r out tba kw output capacitance, c out tba pf i out = 0 ma voltage reference(ext. and int.) reference range, v ref 1.235 v power requirements 4 idd 2 30 ma iaa 3 10.75 ma power supply rejection ratio 0.02 % / % notes 1 guaranteed by characterisation 2 idd or the circuit current, is the continuous current required to drive the digital core 3 iaa is the total current required to supply all dacs including the vref circuitry 4 all dacs on specifications subject to change without notice preliminary technical data
prelim rev d adv7197 preliminary information ?4? (v aa = + 5v 5%, v ref = 1.235 v, r set = 2470 w , r load =300 w. all specifications t min to t max (0 o c to 70 o c) unless otherwise noted, tj max = 110 o c. 5v dynamic-specifications parameter parameter parameter parameter parameter min min min min min typ typ typ typ typ max max max max max units units units units units luma bandwidth tba mhz chroma bandwidth tba mhz signal to noise ratio tba mhz chroma/luma delay inequality tba ns (v aa = +3.3v 5%, v ref = 1.235 v, r set = 2470 w , r load =300 w. all specifications t min to t max (0 o c to 70 o c) unless otherwise noted, tj max = 110 o c. 3.3v dynamic-specifications parameter parameter parameter parameter parameter min min min min min typ typ typ typ typ max max max max max units units units units units luma bandwidth tba mhz chroma bandwidth tba mhz signal to noise ratio tba mhz chroma/luma delay inequality tba ns preliminary technical data
prelim rev d ?5? adv7197 preliminary information 5v timingCspecifications parameter parameter parameter parameter parameter min min min min min typ typ typ typ typ max max max max max units units units units units condition condition condition condition condition mpu port 1 sclock frequency 10 400 khz sclock high pulse width, t 1 0.6 s sclock low pulse width, t 2 1.3 s hold time (start condition), t 3 0.6 s after this period the 1st clock is generated setup time (start condition), t 4 0.6 s relevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition) , t 8 0.6 s analog outputs 1 analog output delay 2 8ns analog output rise/fall time tba ns analog output transition time tba ns analog output skew 0.5 ns clock control and pixel port f clk 74.25 mhz clock high time t 9 1.6 ns clock low time t 10 1.6 ns data setup time t 11 0ns data hold time t 12 2.5 ns control setup time t 11 2.5 ns control hold time t 12 2.0 ns digital output access time t 13 13 ns digital output hold time t 14 12 ns reset low time 1 1.6 ns pipeline delay 16 clock cycles 4:4:4 pixel input notes 1 guaranteed by characterisation 2 output delay measured from the 50% point of the rising edge of clock to the 50% point of dac output full-scale transition specifications subject to change without notice. (v aa = + 5v 5%, v ref = 1.235 v, r set = 2470 w , r load =300 w. all specifications t min to t max (0 o c to 70 o c) unless otherwise noted, tj max = 110 o c. preliminary technical data
prelim rev d adv7197 preliminary information ?6? (v aa = +3.3v 5%, v ref = 1.235 v, r set = 2470 w , r load =300 w. all specifications t min to t max (0 o c to 70 o c) unless otherwise noted, tj max = 110 o c. 3.3v timingCspecifications 1 parameter parameter parameter parameter parameter min min min min min typ typ typ typ typ max max max max max units units units units units condition condition condition condition condition mpu port sclock frequency 10 400 khz sclock high pulse width, t 1 0.6 s sclock low pulse width, t 2 1.3 s hold time (start condition), t 3 0.6 s after this period the 1st clock is generated setup time (start condition), t 4 0.6 s relevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition) , t 8 0.6 s analog outputs analog output delay 2 8ns analog output rise/fall time tba ns analog output transition time tba ns analog output skew 0.25 ns clock control and pixel port f clk 74.25 mhz clock high time t 9 1.5 ns clock low time t 10 2.0 ns data setup time t 11 0ns data hold time t 12 2.0 ns control setup time t 11 3.5 ns control hold time t 12 2.0 ns digital output access time t 13 15 ns digital output hold time t 14 14 ns reset low time 1 2.0 ns pipeline delay 16 clock cycles 4:4:4 pixel input notes 1 guaranteed by characterisation 2 output delay measured from the 50% point of the rising edge of clock to the 50% point of dac output full-scale transition specifications subject to change without notice. preliminary technical data
prelim rev d ?7? adv7197 preliminary information ordering information 1 model package description package option ADV7197KS plastic quad flatpack s-52 absolute maximum ratings* v aa to gnd.............................................................+7v voltage on any digital pin..............gnd-0.5v to v aa +0.5v ambient operating temperature (t a )..........-40c to +85c storage temperature (t s )......................... -65c to +150c junction temperature (t j ).....................................+150c lead temperature (soldering, 10 secs )....................300c vapor phase soldering (1 minute) )..........................220c i out to gnd 1 ....................................................0v to v aa notes * * * * * stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 analog output short circuit to any power supply or common can be of an indefinite duration. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7127 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommende d to avoid performance degradation or loss of functionality. cr[1] cr[2] cr[9] cr[8] cr[3] cr[4] cr[5] cr[7] cr[6] clkin g nd y[0] y[1] y[2] y[3] y[4] y[9] y[5] y[6] y[7] y[8] vdd gnd vref rset dv hsync/sync vsync/tsync dac b comp dac a / y output dac c agnd vaa vaa agnd alsb cr[0] sda scl vdd cb/cr[0] cb/cr[1] cb/cr[2] cb/cr[3] cb/cr[4] cb/cr[5] cb/cr[6] cb/cr[7] cb/cr[8] cb/cr[9] adv7197 re set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 pin id pin configuration preliminary technical data
prelim rev d adv7197 preliminary information ?8? pin function descriptions pin mnemonic input/output function agnd g analog ground gnd g digital ground alsb i ttl address input. this signal sets up the lsb of the mpu address. d v i video blanking control signal input. clkin i pixel clock input. requires a 74.25mhz (74.1758mhz) reference clock. comp o compensation pin for dacs. connect 0.1 m f capacitor from comp pin to v aa . dac a o y analog output. dac b o color component analog output of input data on cr 9-0 input pins. dac c o color component analog output of input data on cb/cr 9-0 input pins. hsync/ sync i hsync , horizontal sync control signal input or sync input control signal in async timing mode. cr 9-0 i 10-bit hdtv input port for color data in 4:4:4 input mode. in 4:2:2 mode this input port is not used. input port for r data when rgb data is input. . cb/cr 9-0 i 10-bit hdtv input port for color data. in 4:2:2 mode the multiplexed crcb data must be input on these pins. input port for b data when rgb data is input. reset i this input resets the on-chip timing generator and sets the adv7197 into default register setting. reset is an active low signal. r set i a 2470 ohms resistor (for input ranges 64-940 and 64-960, (output standards eia770.3)must be connected from this pin to agnd and is used to control the amplitudes of the dac outputs. for input ranges 0 -1023 (output standards rs-170, rs-343a)the r set value must be 2820 ohms. scl i mpu port serial interface clock input sda i/o mpu port serial data input/output vsync/ tsync i vsync , vertical sync control signal input or tsync input control signal in asynctiming mode. v dd p digital power supply v aa p analog power supply v ref i/o optional external voltage reference input for dacs or voltage reference output (1.235v). y9 -y0 i 10-bit hdtv input port for y data. input port for g data when rgb data is input. preliminary technical data
prelim rev d ?9? adv7197 preliminary information functional description functional description functional description functional description functional description digital inputs the digital inputs of the adv7197 are ttl compatible. 30-bit ycrcb or rgb pixel data in 4:4:4 format or 20- bit ycrcb pixel data in 4:2:2 format is latched into the device on the rising edge of each clock cycle at 74.25mhz or 74.1785 in hdtv mode. control signals the adv7197 accepts sync control signals accompanied by valid 4:2:2 or 4:4:4 data. these external horizontal, vertical and blanking pulses (or eav/sav codes) control the insertion of approriate sync information into the output signals. analog outputs the analog y signal is output on dacs a, the color component analog signals on dac b and dac c conforming to eia-770.3 standards rset has a value of 2470 ohms (eia-770.3), rload has a value of 300ohms. for the outputs to conform to rs-170/rs343a standards rset must have a value of 2820ohms. internal test pattern generator the adv7197 can generate a cross hatch pattern (white lines against a black background). additionally the adv7197 can output a uniform color pattern. the color of the lines or uniform field/frame can be programmed by the user. y/ crcb delay the y output and the color component outputs can be delayed wrt the falling edge of the horizontal sync signal by up to 4 clock cycles. preliminary technical data
prelim rev d adv7197 preliminary information ?10? mpu port description. mpu port description. mpu port description. mpu port description. mpu port description. the adv7197 support a two wire serial (i 2 c compatible) microprocessor bus driving multiple peripherals. two inputs serial data (sda) and serial clock (scl) carry information between any device connected to the bus. each slave device is recognized by a unique address. the adv7197 has four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in figure xx. the lsb sets either a read or write operation. logic level "1" corresponds to a read operation while logic level "0" corresponds to a write operation. a1 is set by setting the alsb pin of the adv7197 to logic level "0" or logic level "1". when alsb is set to "0", there is greater input bandwidth on the i2c lines, which allows high speed data transfers on this bus. when alsb is set to "1", there is reduced input bandwidth on the i2c lines, which means that pulses of less than 50ns will not pass into the i2c internal controller. this mode is recommended for noisy systems. fig xx. adv7197 slave address to control the various devices on the bus the following protocol must be followed. first the master initiates a data transfer by establishing a start condition, defined by a high to low transistion on sda whilst scl remains high. this indicates that an address/data stream will follow. all periph- erals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits are tranferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowl- edge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/ w bit deter- mines the direction of the data. a logic "0" on the lsb of the first byte means that the master will write information to the peripheral. a logic "1" on the lsb of the first byte means that the master will read information from the peripheral. the adv7197 acts as a standard slave device on the bus. the data on the sda pin is 8 bits long supporting the 7-bit addresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto-increment allowing data to be written to or read from from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one by one basis without having to update all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, then these cause an immediate jump to the idle condi- tion. during a given scl high period the user should only issue one start condition, one stop condition or a single stop condition followed by a single start condi- tion. if an invalid subaddress is issued by the user, the adv7197 will not issue an acknowledge and will return to the idle condition. if in auto-increment mode, the user exceeds the highest subaddress then the following action will be taken: 1. in read mode, the highest subaddress register con- tents will continue to be output until the master device issues a no-acknowledge. this indicates the end of a read. a no-acknowledge condition is where the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowl- edge will be issued by the adv7197 and the part will return to the idle condition. figure xx. bus data transfer figure 50 illustrates an example of data transfer for a read sequence and the start and stop conditions. figure 51 shows bus write and read sequences. 0 x 10 1 01a1 address control set up by alsb read /w rite control 0write 1 read data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a(s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) a (m ) data p write sequence read sequence a (s) = no-acknowledge by slave a (m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit 1-7 8 9 1-7 8 9 1-7 8 9 p s start addr r/ w ack subaddress ack data ack stop sdata sclock figure xx. write and read sequence preliminary technical data
prelim rev d ?11? adv7197 preliminary information register accesses register accesses register accesses register accesses register accesses the mpu can write to or read from all of the registers of the adv7197 except the subaddress registers which are write only registers. the subaddress register determines which register the next read or write operation accesses. all communications with the part through the bus start with an access to the subaddress register. then a read/ write operation is performed from/to the target address which then increments to the next address until a stop command on the bus is performed. register programming register programming register programming register programming register programming the following section describes the functionality of each register. all registers can be read from as well as written to unless otherwise stated. subaddress register (sr7-sr0) subaddress register (sr7-sr0) subaddress register (sr7-sr0) subaddress register (sr7-sr0) subaddress register (sr7-sr0) the communications register is an eight bit write- only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure xx shows the various operations under the control of the subaddress register. "0" should always be written to sr7. register select (sr6-sr0): register select (sr6-sr0): register select (sr6-sr0): register select (sr6-sr0): register select (sr6-sr0): these bits are set up to point to the required starting address. sr3 sr2 sr1 sr0 sr7 sr6 sr5 zero should be written here sr7 sr4 address 00h 01h 02h 03h 04h 05h 06h 07h 08h sr6 0 0 0 0 0 0 0 0 0 sr5 0 0 0 0 0 0 0 0 0 sr4 0 0 0 0 0 0 0 0 0 sr3 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 mod e register 0 mod e register 1 mod e register 2 mod e register 3 mod e register 4 mod e register 5 color y color cr color cb sr2 sr1 sr0 adv7197 subadress register fig xx. adv7197 subaddress registers preliminary technical data
prelim rev d adv7197 preliminary information ?12? mode register 0 mode register 0 mode register 0 mode register 0 mode register 0 mr0 mr0 mr0 mr0 mr0 (mr07-mr00) (mr07-mr00) (mr07-mr00) (mr07-mr00) (mr07-mr00) (address (sr4-sr0) = 00h) (address (sr4-sr0) = 00h) (address (sr4-sr0) = 00h) (address (sr4-sr0) = 00h) (address (sr4-sr0) = 00h) figure xx shows the various operations under the control of mode register 0. mr0 bit description mr0 bit description mr0 bit description mr0 bit description mr0 bit description output standard selection (mr00-mr01): standard selection (mr00-mr01): standard selection (mr00-mr01): standard selection (mr00-mr01): standard selection (mr00-mr01): these bits are used to select the output levels from the adv7197. if eia 770.3 (mr01-00='00') is selected, the output levels will be: 0mv for blanking level, 700mv for peak white (y channel),+/- 350mv for pr,pb outputs and -300 mv for tri-level sync. if full input range (mr01-00='10') is selected, the output levels will be 700mv for peak white for the y channel, +/- 350 mv for pr, pb outputs and -300mv for sync. this mode is used for rs-170, rs343a standard output com- patibility. sync insertion on the pr, pb channels is optional. for output levels refer to the appendix. input control signals (mr02-mr03): input control signals (mr02-mr03): input control signals (mr02-mr03): input control signals (mr02-mr03): input control signals (mr02-mr03): these control bits are used to select whether data is input with external horizontal, vertical and blanking sync signals or if the data is input with embedded eav/sav codes. an asynchronous timing mode is also available using tsync, sync and dv as input control signals. these timing control signals have to be programmed by the user and are used for any other high definition standard input but smpte274m and smpte296m. the figure below shows an example of how to program the adv7197 to accept a different high definition standard but smpte274m or smpte296m. reserved (mr04): a '0' must be written to this bit. input standard (mr05): select between 1080i or 720p input. dv polarity (mr06): this control bit allows to select the polarity of the dv input control signal to be either active high or active low. this is in order to facilitate interfacing from input devices which use an active high blanking signal output. reserved (mr07): a '0' must be written to this bit. figure xx: async timing mode - programming input control signals for smpte295m compatibility figure xx: dv input control signal in relation to video output signal for smpte296m(720p) 747 748 749 750 1 2 3 4 5 67 8 25 26 27 744 745 display vertical blanking interval hsync vsync dv display // analog out put clk horizontal sync prog ram m able input timing dv set mr06 = '1' sync tsync 66 66 243 1920 81 ab c d active video e xxxxxxxxxxxxxxxxxxxx xxxxx preliminary technical data
prelim rev d ?13? adv7197 preliminary information mr00 mr07 mr06 mr07 zero must be written to this bit mr01 mr02 mr03 mr04 mr05 mr01 mr00 0 0 1 1 output standard selection 0 1 0 1 eia770.3 reserved f ul l i/p rang e reserved mr02 mr03 0 1 mr05 input standard 1080i 720p 0 1 dv polarity mr06 active high active low 0 0 1 1 input control signals 0 1 0 1 hsync/vsync /dv eav/sav tsync/sync/dv reserved zero must be written to this bit mr04 figure xx: mode register 0 the truth table below must be followed when programming the control signals in async timing mode. sync tsync dv 1 -> 0 0 0 or 1 50% point of falling edge of tri-level horizontal sync signal, a 0 0 -> 1 0 or 1 25% point of rising edge of tri-level horizontal sync signal, b 0 -> 1 0 or 1 0 50% point of falling edge of tri-level horizontal sync signal, c 1 0 or 1 0 -> 1 50% start of active video, d 1 0 or 1 1 -> 0 50% end of active video, e preliminary technical data
prelim rev d adv7197 preliminary information ?14? mode register 1 mode register 1 mode register 1 mode register 1 mode register 1 mr1 mr1 mr1 mr1 mr1 (mr17-mr10) (mr17-mr10) (mr17-mr10) (mr17-mr10) (mr17-mr10) (address (sr4-sr0) = 01h) (address (sr4-sr0) = 01h) (address (sr4-sr0) = 01h) (address (sr4-sr0) = 01h) (address (sr4-sr0) = 01h) figure xx shows the various operations under the control of mode register 1. mr1 bit description mr1 bit description mr1 bit description mr1 bit description mr1 bit description pixel data enable (mr10): pixel data enable (mr10): pixel data enable (mr10): pixel data enable (mr10): pixel data enable (mr10): when this bit is set to "0", the pixel data input to the adv7197 is blanked such that a black screen is output from the dacs. when this bit is set to "1", pixel data is accepted at the input pins and the adv7197 outputs to the standard set in 'output standard selection' (mr01-00). input format (mr11): it is possible to input data in 4:2:2 format or in 4:4:4 format. testpattern enable (mr12): enables or disables the internal test pattern generator. testpattern hatch/frame (mr13): if this bit is set to '0', a cross hatch test pattern is output from the adv7197. the cross hatch test pattern can be used to test monitor convergence. if this bit is set to '1', a uniform colored frame/field test pattern is output from the adv7197. the color of the lines or the frame/field is by default white but can be programmed to be any color using the color y, color cr, color cb registers. mr10 mr17 mr16 pixel data enable mr10 mr11 mr12 mr13 mr14 mr15 inpu t f orm a t mr12 test pattern enable mr12 test pattern hatch/frame mr13 vbi_open 0disable 1 enable mr14 mr17 0hatch 1field/frame 0 4:4 :4 yc rc b 1 4:2 :2 yc rc b 0disable 1 enable 0disable 1 enable zero must be written to these bits figure xx: mode register 1 vbi open (mr14): this bit enables or disables the facility of vbi data insertion during the vertical blanking interval. for this purpose lines 7-20 in 1080i and lines 6-25 in 720p can be used for vbi data insertion. reserved (mr15 -mr17): a '0' must be written to these bits. preliminary technical data
prelim rev d ?15? adv7197 preliminary information mr22 mr23 mr26 mr25 mr24 mr20 mr27 mr21 mr26-27 a zero must be written to these bits color delay mr25 mr24 mr23 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 pclk 1 pclk 2 pclk 3 pclk 4 pclk y delay mr22 mr21 mr20 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 pclk 1 pclk 2 pclk 3 pclk 4 pclk mode register 2 mode register 2 mode register 2 mode register 2 mode register 2 mr1 mr1 mr1 mr1 mr1 (mr27-mr20) (mr27-mr20) (mr27-mr20) (mr27-mr20) (mr27-mr20) (address (sr4-sr0) = 02h) (address (sr4-sr0) = 02h) (address (sr4-sr0) = 02h) (address (sr4-sr0) = 02h) (address (sr4-sr0) = 02h) figure xx shows the various operations under the control of mode register 2. mr2 bit description mr2 bit description mr2 bit description mr2 bit description mr2 bit description y delay (mr20-22): (mr20-22): (mr20-22): (mr20-22): (mr20-22): with theses bits it is possible to delay the y signal with respect to the falling edge of the horizontal sync signal by up to 4 pixel clock cycles. figure xx demonstrates this facility. color delay (mr23-25): (mr23-25): (mr23-25): (mr23-25): (mr23-25): with theses bits it is possible to delay the color signals with respect to the falling edge of the horizontal sync signal by up to 4 pixel clock cycles. figure xx demonstrates this facility. reserved (mr26-27): a '0' must be written to these bits. prpb d ela y y out put y del ay prpb outputs max delay max delay no delay no delay figure xx: y and color delay figure xx: mode register 2 preliminary technical data
prelim rev d adv7197 preliminary information ?16? mr31 mr37 mr32 mr33 mr36 mr35 mr34 mr30 dac b control mr34 0 power-down 1normal mr32-31 zero must be written to this bit dac a control mr33 mr37-36 dac c control mr35 0 1 0 1 pow er-down normal power-down normal zer0 must be written to these bits mode register 3 mode register 3 mode register 3 mode register 3 mode register 3 mr3 mr3 mr3 mr3 mr3 (mr37-mr30) (mr37-mr30) (mr37-mr30) (mr37-mr30) (mr37-mr30) (address (sr4-sr0) = 03h) (address (sr4-sr0) = 03h) (address (sr4-sr0) = 03h) (address (sr4-sr0) = 03h) (address (sr4-sr0) = 03h) figure xx shows the various operations under the control of mode register 3. mr3 bit description mr3 bit description mr3 bit description mr3 bit description mr3 bit description reserved(mr31-32): a "0" must be written to these bits. dac a control (mr33): setting this bit to "1" enables dac a , otherwise this dac is powered down. dac b control (mr34): setting this bit to "1" enables dac b , otherwise this dac is powered down. dac c control (mr35): setting this bit to "1" enables dac c , otherwise this dac is powered down. reserved (mr36-37): a '0' must be written to these bits. figure xx: mode register 3 preliminary technical data
prelim rev d ?17? adv7197 preliminary information m r47 m r42 m r43 m r46 m r45 m r44 m r40 ti mi ng reset m r40 m r41 zero must be w ri tten to these regi sters m r47-mr41 mode register 4 mode register 4 mode register 4 mode register 4 mode register 4 mr4 mr4 mr4 mr4 mr4 (mr47-mr40) (mr47-mr40) (mr47-mr40) (mr47-mr40) (mr47-mr40) (address (sr4-sr0) = 04h) (address (sr4-sr0) = 04h) (address (sr4-sr0) = 04h) (address (sr4-sr0) = 04h) (address (sr4-sr0) = 04h) figure xx shows the various operations under the control of mode register 4. mr4 bit description mr4 bit description mr4 bit description mr4 bit description mr4 bit description timing reset (mr40): (mr40): (mr40): (mr40): (mr40): toggling mr40 from low to high and low again resests the internal horizontal and vertical timing counters. figure xx: mode register 4 preliminary technical data
prelim rev d adv7197 preliminary information ?18? mr57 mr52 mr53 mr56 mr55 mr54 mr50 mr51 color output swap mr53 0 1 disable enable mr54-57 mr50 reserved for revision code zero must be written to these bits rgb mode mr51 0 1 disable enable sync on prpb mr52 0 1 disable enable mode register 5 mode register 5 mode register 5 mode register 5 mode register 5 mr5 mr5 mr5 mr5 mr5 (mr57-mr50) (mr57-mr50) (mr57-mr50) (mr57-mr50) (mr57-mr50) (address (sr4-sr0) = 05h) (address (sr4-sr0) = 05h) (address (sr4-sr0) = 05h) (address (sr4-sr0) = 05h) (address (sr4-sr0) = 05h) figure xx shows the various operations under the control of mode register 5. mr5 bit description mr5 bit description mr5 bit description mr5 bit description mr5 bit description reserved (mr50): (mr50): (mr50): (mr50): (mr50): this bit is reserved for the revision code. rgb mode (mr51): when rgb mode is enabled (mr51="1") the adv7197 accepts unsigned binary rgb data at its input port. this control is also available in async timing mode. figure xx: mode register 5 sync on prpb (mr52): by default the color component output signals pr, pb do not contain any horizontal sync pulses. they can be inserted when mr52="1". this control is not available in rgb mode. color output swap (mr53): by default dac b is configured as the pr output and dac c as the pb output. in setting this bit to "1" the dac outputs can be swapped around so that dac b outputs pb and dac c outputs pr. the table below demonstrates this in more detail. this control is also available in rgb mode. in 4:4:4 input mode color data mr53 analog output input on pins: signal: cr 9-0 0 dac b cb/cr 9-0 0 dac c cr 9-0 1 dac c cb/cr 9-0 1 dac b in 4:2:2 input mode color data mr53 analog output input on pins: signal: cr 9-0 0 or 1 not operational cb/cr 9-0 0 dac c (pb) cb/cr 9-0 1 dac c (pr) table xx relationship between color input pixel port, mr53 and dac b, dac c outputs preliminary technical data
prelim rev d ?19? adv7197 preliminary information cy6 cy5 cy3 cy1 cy4 cy2 cy0 cy7 color y value ccb6 ccb5 ccb3 ccb1 ccb4 ccb2 ccb0 ccb7 color cb value ccr6 ccr5 ccr3 ccr1 ccr4 ccr2 ccr0 ccr7 color cr value color y color y color y color y color y cy cy cy cy cy (cy7-cy0) (cy7-cy0) (cy7-cy0) (cy7-cy0) (cy7-cy0) (address (sr4-sr0) = 06h) (address (sr4-sr0) = 06h) (address (sr4-sr0) = 06h) (address (sr4-sr0) = 06h) (address (sr4-sr0) = 06h) color cr color cr color cr color cr color cr ccr ccr ccr ccr ccr (ccr7-ccr0) (ccr7-ccr0) (ccr7-ccr0) (ccr7-ccr0) (ccr7-ccr0) (address (sr4-sr0) = 07h) (address (sr4-sr0) = 07h) (address (sr4-sr0) = 07h) (address (sr4-sr0) = 07h) (address (sr4-sr0) = 07h) color cb color cb color cb color cb color cb ccb ccb ccb ccb ccb (ccb7-ccb0) (ccb7-ccb0) (ccb7-ccb0) (ccb7-ccb0) (ccb7-ccb0) (address (sr4-sr0) = 08h) (address (sr4-sr0) = 08h) (address (sr4-sr0) = 08h) (address (sr4-sr0) = 08h) (address (sr4-sr0) = 08h) these three 8-bit wide registers are used to program the output color of the internal testpattern generator, be it the lines of the cross hatch pattern or the uniform field testpattern. the standard used for the values for y and the color difference signals to obtain white, black and the saturated primary and complementary colors conforms to the itu-r bt 601-4 standard. the table below shows sample color values to be pro- grammed into the color registers. color y value color cr value color cb value white black red green blue yellow cyan magenta 235 (eb) 16 (10) 81 (51) 145 (91) 41 (29) 210 (d2) 170 (aa) 106 (6a) 128 (80) 128 (80) 240 (f0) 34 (22) 110 (6e) 146 (92) 16 (10) 222 (de) 128 (80) 128 (80) 90 (5a) 54 (36) 240 (f0) 16 (10) 166 (a6) 202 (ca) sample color figure xx sample color values figure xx. color y register figure xx. color cr register figure xx. color cb register preliminary technical data
prelim rev d adv7197 preliminary information ?20? dac termination and layout considerations dac termination and layout considerations dac termination and layout considerations dac termination and layout considerations dac termination and layout considerations voltage reference the adv7197 contains an onboard voltage reference. the vref pin is normally terminated to vaa throught a 0.1uf capacitor when the internal vref is used. alternatively, the adv7197 can be used with an external vref (ad589). resistor rset is connected between the rset pin and agnd and is used to control the full scale output current and therefore the dac voltage output levels. for full scale output rset must have a value of 2470ohms. rload has a value of 300ohms. when an input range of 0-1023 is selected the value of rset must be 2820ohms. the adv7197 has three analog outputs, corresponding to y, pr, pb video signals. each one of the prpb dacs is capable of an output current of 2.66ma, the y dac provides 4.33ma output current. the dacs must be used with external buffer circuits in order to provide sufficient current to drive an output device. suitable op-amps are the ad8009, ad8002 or the ad8001current feedback amplifiers. pc board layout considerations the adv7197 is optimally designed for lowest noise performance, both radiated and conducted noise. to complement the excellent noise performance of the adv7197, it is imperative that great care be given to the pc board layout. the layout should be optimized for lowest noise on the adv7197 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of vaa and agnd and vdd and dgnd pins should be kept as short as possible to minimized inductive ringing. it is recommended that a four-layer printed circit board is used. with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. placement of components should consider to seperate noisy circuits, such as crystal clocks, high speed logic circuitry and analog circuitry. there should be a seperate analog ground plane (agnd) and a seperate digital ground plane (gnd). power planes should encompass a digital power plane (vdd) and a analog power plane (vaa). the analog power plane should contain the dacs and all associated circuitry, vref circuitry. the digital power plane should contain all logic circuitry. the analog and digital power planes should be individually connected to the common power plane at one single point through a suitable filtering device, such as a ferrite bead. dac output traces on a pcb should be treated as transmission lines. it is recommended that the dacs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches. the dac termination resistors should be placed as close as possible to the dac outputs and should overlay the pcb's ground plane. as well as minimizing reflectitons, short analog output traces will reduce noise pickup due to neighbouring digital circuitry. supply decoupling noise on the analog power plane can be further reduced by the use of decoupling capacitors. optimum performance is achieved by the use of 0.1uf ceramic capacitors. each of group of vaa or vdd pins should be individually decoupled to ground. this should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. digital signal interconnect the digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the adv7197 should be avoided to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane. analog signal interconnect the adv7197 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. for optimum performance, the analog outputs should each be source and load terminated, as shown in the figure below.the termination resistors should be as close as possible to the adv7197 to minimize reflections. any unused inputs should be tied to ground. preliminary technical data
prelim rev d ?21? adv7197 preliminary information figure xx: adv7197 circuit layout 1,12 v dd 10nf 0.1f +5v +5v 0.1f 37 comp 39 v ref 300r dac a dac b 300r 36 pr (v) output 5k +5v 31 5k +5v mpu bus 30 sda scl 100r 100r 25 40 29 27 28 vsync/ tsync dv/clkout 13,52 gnd 41 pow er supply decoupling for each pow er supply group 4k7 +5v 74.25mhz or 74.1758mhzclock alsb reset clkin adv7197 "un used inpu ts should be grounded" 4k7 +5v 4.7uf 6.3v 2k47 or 2k82 38 r set 300r 32 dac c pb (u ) o utput 34 + cb/cr0-cb/cr9 cr0-cr9 y0-y9 y output hsync/ sync 24, 35 v aa 10nf 0.1f +5v agnd 26, 33, preliminary technical data
prelim rev d adv7197 preliminary information ?22? figure xx output buffer and optional filter video output buffer and optional output filter video output buffer and optional output filter video output buffer and optional output filter video output buffer and optional output filter video output buffer and optional output filter output buffering is necessary in order to drive output devices, such as hdtv monitors. analog devides produces a range of suitable op ams for this application. suitable op amps would be the ad8009,ad8002 or ad8001. more information on line driver buffering circuits is given in the relevant op amp datasheets. an optional analog reconstruction lpf might be required as an antialias filter if the adv7197 is connected to a device which requires this filtering. the eval adv7196/7 eb evaluation board uses the ml6426 microlinear ic, which provides buffering and low-pass filtering for hdtv applications. the eval adv7196/7eb reva evaluation board uses the ad8009 as a buffer and a 6th order chebychev filter as a lpf. the application note, anxxx, describes in detail these two designs and should be consulted when designing external filter and buffers for analog devices video encoders. + 0.1 m f 10 m f 0.1 m f10 m f + -5v +5v 75r 75r coax 75r ad8009 rf rg 300r adv7197 300r 300r dac a dac b dac c lpf lpf lpf + 0.1 m f 10 m f 0.1 m f10 m f + -5v +5v 75r 75r coax 75r ad8009 rf rg + 0.1 m f 10 m f 0.1 m f10 m f + -5v +5v 75r 75r coax 75r ad8009 rf rg hdtv monitor 7 6 7 6 4 2 7 6 preliminary technical data
prelim rev d ?23? adv7197 preliminary information figure xx eia 770.3 standard output signals(1080i, 720p) figure xx output levels for full i/p selection 70 0mv 0mv -30 0mv output voltage. y - o utp ut leve ls for full i/p se lec- tion ac tive vi d eo inp ut c o de 700mv 0mv -300mv output voltage. p rp b - o utpu t le vels for fu ll i /p s elec tion ac ti ve vid eo inp ut c o de 1023 64 1023 64 70 0mv 0mv -300mv output voltage. eia-770.3, standard fo r y. ac ti ve vid eo 350mv 0mv -350mv output voltage. -300mv eia- 770.3, standard for pr/p b ac tive vid eo 30 0mv 30 0mv inp ut c o de 940 64 960 512 64 preliminary technical data
prelim rev d adv7197 preliminary information ?24? figure xx 4:2:2 input data format timing diagram figure xx 4:4:4 ycrcb input data format timing diagram t 9 t 11 clock pixel input data t 10 t 12 y0 y1 y2 ... ... yxxx yxx x cb0 cr0 cb1 cr1 ... cbxxx crxxx t9 - clock high time t10 - clock low time t11 - data setup time t12 - data hold time t 9 t 11 clock pixel input data t 10 t 12 y0 y1 y2 ... ... yxxx yxx x cb0 cb1 cb2 cb3 ... cbxxx crxxx t9 - clock igh time t10 - clock ow time t11 - data setup time t12 - data hold time cr0 cr1 cr2 cr3 ... crxxx crxxx preliminary technical data
prelim rev d ?25? adv7197 preliminary information hsync vsync dv pixel data yy yy cr cr cr cr cb b c b c b figure xx input timing diagram figure xx 4:4:4 rgb input data format timing diagram t 9 t 11 clock pixel input data t 10 t 12 r0 r1 r2 ... ... rxxx rxxx g0 g1 g2 g3 ... gxxx gxxx t9 - clock igh time t10 - clock ow time t11 - data setup time t12 - data hold time b0 b1 b2 b3 ... bxxx b preliminary technical data
prelim rev d adv7197 preliminary information ?26? figure xx eav/sav input data timing diagram - smpte 274m (1080i) c b y c r c r eav code sav code ancillary data (optional) or blanking code 4 clock 4 clock analog waveform input pixels y digital active line sample number smpte274m // // // // digital horizontal blanking 0 h datum f f 0 0 0 0 f v h* fvh* = fvh and parity bits sav/eav : line 1 - 562 : f=0 sav/eav: line 563 - 1125 : f=1 sav/eav: line 1-20; 561-583;1124-1125: v=1 sav/eav: line 21-560;584-1123: v=0 f f 0 0 0 0 f v h* 2 1 1 2 2 1 1 6 2 1 5 6 0 2 1 9 9 4 4 1 9 2 2 1 1 1 1 8 8 4t 272t 4t 1920t preliminary technical data
prelim rev d ?27? adv7197 preliminary information 747 748 749 750 1 2 3 4 5 67 8 25 26 27 744 745 display vertical blanking interval 1124 1125 1 2 3 4 5 67 8 20 21 22 560 display vertical blanking interval 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 display vertical blanking interval field 1 field 2 figure xx smpte 296m (720p) figure xx smpte 274m (1080i) preliminary technical data
prelim rev d adv7197 preliminary information ?28? figure 1. mpu port timing diagram t 3 t 1 t 6 t 2 t 7 t 5 t 3 t 4 t 8 sda scl preliminary technical data
prelim rev d ?29? adv7197 preliminary information 52-lead plastic quad flatpack (s-52) top view (pins d own) 1 13 14 27 26 39 40 52 pin 1 0.014 (0.35) 0.010 (0.25) 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91) 0.5 57 (14 .1 5) 0.5 37 (13 .6 5) 0.3 98 (10 .1 1) 0.3 90 (9. 91) 0.0256 (0.65) bsc 0.082 (2.09) 0.078 (1.97) 0.012 (0.30) 0.006 (0.15) 0.008 (0.20) 0.006 (0.15) seating plane 0.037 (0.95) 0.026 (0.65) 0.094 (2.39) 0.084 (2.13) outline dimensions dimensions shown in inches and (mm). preliminary technical data

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